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PHU101NQ03LT
N-channel TrenchMOS logic level FET
Rev. 04 -- 30 June 2009 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low on-state resistance Simple gate drive required due to low gate charge Suitable for logic level gate drive sources
1.3 Applications
DC-to-DC convertors
1.4 Quick reference data
Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 C; VGS = 10 V; see Figure 1; see Figure 3 Tmb = 25 C; see Figure 2 Min Typ Max 30 75 166 Unit V A W drain-source voltage Tj 25 C; Tj 175 C drain current total power dissipation gate-drain charge Symbol Parameter
Dynamic characteristics QGD VGS = 5 V; ID = 50 A; VDS = 15 V; Tj = 25 C; see Figure 11 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 9; see Figure 10 8 nC
Static characteristics RDSon drain-source on-state resistance 4.5 5.5 m
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pin 1 2 3 mb Pinning information Symbol G D S D Description gate drain source mounting base; connected to drain
mb
D
Simplified outline
Graphic symbol
G
mbb076
S
1
2
3
SOT533 (IPAK)
3. Ordering information
Table 3. Ordering information Package Name PHU101NQ03LT IPAK Description plastic single-ended package (IPAK); 3 leads (in-line) Version SOT533 Type number
PHU101NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
2 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current VGS = 10 V; Tmb = 100 C; see Figure 1 VGS = 10 V; Tmb = 25 C; see Figure 1; see Figure 3 IDM Ptot Tstg Tj VGSM peak drain current total power dissipation storage temperature junction temperature peak gate-source voltage source current peak source current pulsed; = 25 %; Tj 150 C; tp 50 s tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2 Conditions Tj 25 C; Tj 175 C Tj 25 C; Tj 175 C; RGS = 20 k Min -20 -55 -55 -25 Max 30 30 20 75 75 240 166 175 175 25 Unit V V V A A A W C C V
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode IS ISM EDS(AL)S Tmb = 25 C tp 10 s; pulsed; Tmb = 25 C 75 240 185 A A mJ
Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 43 A; Vsup 15 V; drain-source avalanche unclamped; tp = 0.19 ms; RGS = 50 energy
120 Ider (%) 80
03ai19
120 Pder (%) 80
03aa16
40
40
0 0 50 100 150 200 Tmb (C)
0 0 50 100 150 Tmb (C) 200
Fig 1.
Normalized continuous drain current as a function of mounting base temperature
Fig 2.
Normalized total power dissipation as a function of mounting base temperature
PHU101NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
3 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
103 ID (A) Limit RDSon = VDS / ID tp = 10 s 100 s
03ai21
102
DC 10
1 ms 10 ms
1 1 10 VDS (V)
102
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHU101NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
4 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5. Symbol Rth(j-mb) Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to mounting base thermal resistance from junction to ambient Conditions see Figure 4 vertical in free air Min Typ 70 Max 0.19 Unit K/W K/W
10 Zth(j-mb) (K/W) 1 = 0.5 0.2 10-1 0.1 0.05 0.02 10-2 single pulse
tp T P
03ai20
=
tp T
t
10-3 10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHU101NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
5 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 A; VGS = 0 V; Tj = -55 C ID = 250 A; VGS = 0 V; Tj = 25 C ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 7; see Figure 8 ID = 1 mA; VDS = VGS; Tj = 175 C; see Figure 7; see Figure 8 ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 7; see Figure 8 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 30 V; VGS = 0 V; Tj = 25 C VDS = 30 V; VGS = 0 V; Tj = 175 C VGS = 20 V; VDS = 0 V; Tj = 25 C VGS = -20 V; VDS = 0 V; Tj = 25 C VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 9; see Figure 10 VGS = 5 V; ID = 25 A; Tj = 175 C; see Figure 9; see Figure 10 VGS = 5 V; ID = 25 A; Tj = 25 C; see Figure 9; see Figure 10 Dynamic characteristics QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 13 IS = 10 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 25 V; Tj = 25 C VDS = 15 V; RL = 0.6 ; VGS = 4.5 V; RG(ext) = 5.6 ; Tj = 25 C; ID = 25 A VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 12 ID = 50 A; VDS = 15 V; VGS = 5 V; Tj = 25 C; see Figure 11 23 10.5 8 2180 600 225 23 90 37 33 0.85 37 33 1.2 nC nC nC pF pF pF ns ns ns ns V ns nC Min 27 30 0.6 1 Typ 1.9 0.05 10 10 4.5 10.5 5.8 Max 2.9 2.5 1 500 100 100 5.5 13.5 7.5 Unit V V V V V A A nA nA m m m
Static characteristics
Source-drain diode
PHU101NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
6 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
80 ID (A) 60
03ai22
VGS (V) = 10 Tj = 25 C
5 4.5
4 3.8
80 ID (A) 60
03ai24
3.6
40
3.4
40
3.2 20 3 2.8 0 0 0.2 0.4 0.6 0.8 VDS (V) 1 0 0 1 2 3 V (V) 4 GS 20 175 C Tj = 25 C
Fig 5.
Output characteristics: drain current as a function of drain-source voltage; typical values
03ai29
Fig 6.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
03ai28
3.2 VGS(th) (V) max 2.4 typ 1.6
10-1 ID (A) 10-2
10-3
min
typ
max
10-4 min 0.8 10-5
0 -60
10-6 0 60 120 Tj (C) 180 0 0.8 1.6 2.4 VGS(V) 3.2
Fig 7.
Gate-source threshold voltage as a function of junction temperature
Fig 8.
Sub-threshold drain current as a function of gate-source voltage
PHU101NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
7 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
16 RDSon (m) 12
03ai23
Tj = 25 C
2 a 1.5
03af18
VGS (V) = 3.8
4 8 1
4.5 5 10
4
0.5
0 0 20 40 60 ID (A) 80
0 -60
0
60
120
Tj (C)
180
Fig 9.
Drain-source on-state resistance as a function of drain current; typical values
Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature
104
03ai26
10 VGS (V) 8 ID = 50 A Tj = 25 C VDS = 15 V
03ai27
C (pF) Ciss
6 103 4 Coss
2
Crss
0 0 10 20 30 40 50 QG (nC)
102 10-1
1
10
VDS (V)
102
Fig 11. Gate-source voltage as a function of gate charge; typical values
Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PHU101NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
8 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
80 IS (A) 60 VGS = 0 V
03ai25
40
20 175 C Tj = 25 C
0 0 0.3 0.6 0.9 VSD (V) 1.2
Fig 13. Source current as a function of source-drain voltage; typical values
PHU101NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
9 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended package (IPAK); 3 leads (in-line) SOT533
E E1 A1
A
D1 mounting base D2
L1 Q
L
1
2
3
e1 e
b
w
M
c
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.93 0.46 b 0.89 0.71 c 0.56 0.46 D1 1.10 0.96 D2 6.22 5.98 E 6.73 6.47 E1 e e1 L 9.6 9.2 L1 (2) max 2.7 Q 1.1 1.0 w 0.3
2.285 5.21 4.57 5.00 BSC (1) BSC (1)
Notes 1. Basic spacing between centers. 2. Terminal dimensions are uncontrolled within zone L1. OUTLINE VERSION SOT533 REFERENCES IEC JEDEC TO-251 JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-02-14
Fig 14. Package outline SOT533 (IPAK)
PHU101NQ03LT_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
10 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history Release date 20090630 Data sheet status Product data sheet Change notice Supersedes PHP_PHU101NQ03LT_3 Document ID PHU101NQ03LT_4 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Type number PHU101NQ03LT separated from data sheet PHP_PHU101NQ03LT_3. Product data sheet Product data Product data CPC # 200309016 PHP_PHU101NQ03LT-02 PHP_PHD_PHB_PHU101 NQ03LT-01 -
PHP_PHU101NQ03LT_3
20051117
PHP_PHU101NQ03LT-02 20030225 (9397 750 10927) PHP_PHD_PHB_PHU101 20020220 NQ03LT-01 (9397 750 09307)
PHU101NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
11 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
9.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PHU101NQ03LT_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 30 June 2009
12 of 13
NXP Semiconductors
PHU101NQ03LT
N-channel TrenchMOS logic level FET
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 June 2009 Document identifier: PHU101NQ03LT_4

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